TSMC Completes 5nm Node Design, Node in Risk Production
TSMC has announced the completion of its 5nm design infrastructure, with support for a wide variety of processor development. The company has finished tool development to support both next-generation low-power SoCs and high-performance computing (HPC) applications, as well as specialized products intended for the AI market.
While TSMC is talking about the 5nm node as a major step forward for its entire ecosystem, it’s not entirely clear which products will adopt it outside of the mobile markets. The node is targeting a 45 percent area reduction over 7FF but only promises a 15 percent performance improvement at the same power. Anandtech has previously quoted TSMC as predicting a 20 percent power improvement iso frequency, but that claim isn’t actually repeated in the most recent TSMC report on the node. We’re assuming, however, that 20 percent remains the target.
TSMC will be able to use EUV on 14 layers, a substantial improvement over EUV at 7nm, which will only use that technology on four non-critical layers (contacts and vias).
“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”
The problem with trying to talk about EUV is that the technology is both critical to the future of semiconductor manufacturing and yet not expected to deliver enormous performance improvements in and of itself. Standing up EUV manufacturing and putting it into high volume production has literally been a goal the semiconductor industry has worked towards for years, and you can make an argument that the first real debut for the technology as an essential component of lithography happens at 5nm, not 7nm. After several decades of collective work, TSMC seems likely to cross the 5nm finish line first. But while it’s an essential and important technological milestone, EUV isn’t a technology that’s going to drive major silicon performance or power improvements. As such, it wouldn’t necessarily be surprising if 5nm — or at least, first-gen 5nm — was mostly a mobile play.
Samsung is debuting EUV in its 7nm node off the bat but, like TSMC, will only use EUV for contacts and vias at its initial node. TSMC looks to be the first company that will put the technology into critical metal layers, beating both Intel and its Korean rival to the punch.
- Report: TSMC 7nm Utilization Improves on Orders From AMD, HiSilicon
- Report Claims Apple Will Use TSMC for 5nm in 2020
- TSMC: Weak 2019 Demand, but 5nm Set for 2020 Volume Manufacturing