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How Are Process Nodes Defined?

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We talk a lot about process nodes at ExtremeTech, but we don’t often refer back to what a process node technically is. With Intel’s 10nm node moving towards production, I’ve noticed an uptick in conversations around this issue and confusion about whether TSMC and Samsung possess a manufacturing advantage over Intel (and, if they do, how large an advantage they possess).

Process nodes are typically named with a number followed by the abbreviation for nanometer: 32nm, 22nm, 14nm, etc. There is no fixed, objective relationship between any feature of the CPU and the name of the node. This was not always the case. From roughly the 1960s through the end of the 1990s, nodes were named based on their gate lengths. This chart from IEEE shows the relationship:

For a long time, gate length (the length of the transistor gate) and half-pitch (half the distance between two identical features on a chip) matched the process node name, but the last time this was true was 1997. The half-pitch continued to match the node name for several generations but is no longer related to it in any practical sense. In fact, it’s been a very long time since our geometric scaling of processor nodes actually matched with what the curve would look like if we’d been able to continue actually shrinking feature sizes.

Well below 1nm before 2015? Pleasant fantasy.

If we’d hit the geometric scaling requirements to keep node names and actual feature sizes synchronized, we’d have plunged below 1nm manufacturing six years ago. The numbers that we use to signify each new node are just numbers that companies pick. Back in 2010, the ITRS (more on them in a moment) referred to the technology chum bucket dumped in at every node as enabling “equivalent scaling.” As we approach the end of the nanometer scale, companies may begin referring to angstroms instead of nanometers, or we may simply start using decimal points. When I started work in this industry it was much more common to see journalists refer to process nodes in microns instead of nanometers — 0.18-micron or 0.13-micron, for example, instead of 180nm or 130nm.

How the Market Fragmented

Semiconductor manufacturing involves tremendous capital expenditure and a great deal of long-term research. The average length of time between when a new technological approach is introduced in a paper and when it hits widescale commercial manufacturing is on the order of 10-15 years. Decades ago, the semiconductor industry recognized that it would be to everyone’s advantage if a general roadmap existed for node introductions and the feature sizes those nodes would target. This would allow for the broad, simultaneous development of all the pieces of the puzzle required to bring a new node to market. For many years, the ITRS — the International Technology Roadmap for Semiconductors — published a general roadmap for the industry. These roadmaps stretched over 15 years and set general targets for the semiconductor market.

Image by Wikipedia

The ITRS was published from 1998-2015. From 2013-2014, the ITRS reorganized into the ITRS 2.0, but soon recognized that the scope of its mandate — namely, to provide “the main reference into the future for university, consortia, and industry researchers to stimulate innovation in various areas of technology” required the organization to drastically expand its reach and coverage. The ITRS was retired and a new organization was formed called IRDS — International Roadmap for Devices and Systems — with a much larger mandate, covering a wider set of technologies.

This shift in scope and focus mirrors what’s been happening across the foundry industry. The reason we stopped tying gate length or half-pitch to node size is that they either stopped scaling or began scaling much more slowly. As an alternative, companies have integrated various new technologies and manufacturing approaches to allow for continued node scaling. At 40/45nm, companies like GF and TSMC introduced immersion lithography. Double-patterning was introduced at 32nm. Gate-last manufacturing was a feature of 28nm. FinFETs were introduced by Intel at 22nm and the rest of the industry at the 14/16nm node.

Companies sometimes introduce features and capabilities at different times. AMD and TSMC introduced immersion lithography at 40/45nm, but Intel waited until 32nm to use that technique, opting to roll out double-patterning first. GlobalFoundries and TSMC began using double-patterning more at 32/28nm. TSMC used gate-last construction at 28nm, while Samsung and GF used gate-first technology. But as progress has gotten slower, we’ve seen companies lean more heavily on marketing, with a greater array of defined “nodes.” Instead of waterfalling over a fairly large numerical space (90, 65, 45) companies like Samsung are launching nodes that are right on top of each other, numerically speaking:

I think you can argue that this product strategy isn’t very clear, because there’s no way to tell which process nodes are evolved variants of earlier nodes unless you have the chart handy.

While node names are not tied to any specific feature size, and some features have stopped scaling, semiconductor manufacturers are still finding ways to improve on key metrics. That’s genuine engineering improvement. But because advantages are harder to come by now, and take longer to develop, companies are experimenting more with what to call those improvements. Samsung, for example, is deploying many more node names than it used to. That’s marketing.

Why Do People Claim Intel 10nm and TSMC/Samsung 7nm Are Equivalent?

Because the manufacturing parameters for Intel’s 10nm process are very close to the values TSMC and Samsung use for what they call a 7nm process. The chart below is drawn from WikiChip, but it combines the known feature sizes for Intel’s 10nm node with the known feature sizes for TSMC’s and Samsung’s 7nm node. As you can see, they’re very similar:

Image by ET, compiled from data at WikiChip

The delta 14nm / delta 10nm column shows how much each company scaled a particular feature down from its previous node. Intel and Samsung have a tighter minimum metal pitch than TSMC does, but TSMC’s high-density SRAM cells are smaller than Intel’s, likely reflecting the needs of different customers at the Taiwanese foundry. Samsung’s cells, meanwhile, are even smaller than TSMC’s. Overall, however, Intel’s 10nm process hits many of the key metrics as what both TSMC and Samsung are calling 7nm.

Individual chips may still have features that depart from these sizes due to particular design goals. The information manufacturers provide on these numbers are for a typical expected implementation on a given node, not necessarily an exact match for any specific chip.

There have been questions about how closely Intel’s 10nm+ process (used for Ice Lake) reflects these figures (which I believe were published for Cannon Lake). It’s true that the expect specifications for Intel’s 10nm node may have changed slightly, but 14nm+ was an adjustment from 14nm as well. Intel has stated that it is still targeting a 2.7x scaling factor for 10nm relative to 14nm, so we’ll hold off on any speculation about how 10nm+ may be slightly different.

Pulling It All Together

The best way to understand the meaning of a new process node is to think of it as an umbrella term. When a foundry talks about rolling out a new process node, what they are saying boils down to this:

“We have created a new manufacturing process with smaller features and tighter tolerances. In order to achieve this goal, we have integrated new manufacturing technologies. We refer to this set of new manufacturing technologies as a process node because we want an umbrella term that allows us to capture the idea of progress and improved capability.”

Any additional questions on the topic? Drop them below and I’ll answer them.

Now Read: 

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  • Ice Lake Benchmarks Paint a Complex Picture for Intel’s Latest CPU

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